design verification engineer

Design Verification Engineer

We are building fresh new chip design and verification team with one of the most important companies in this area and we are looking for a remote, full-time Design Verification Engineer with 5+ years of experience.


In this role you will


  • Be responsible for SOC Functional verification and sign-off.
  • Help define a comprehensive verification methodology for SOCs
  • Test plan development, coverage goals, simulation   performance
     enhancements and regression methodology using Verilog,
     System Verilog, UVM, C/C++, Perl/Python.
  • Evaluate tradeoffs between block vs full chip verification
    scope with directed vs constrained random tests to
    define verification test bench boundaries.
  • Develop system level verification strategy.
  • Develop highly reusable system level test plan content and execute the content.
  • Architect the reusable and scalable test bench.
  • Integrate VIPs for AHB/APB/I3C/SPI/UART/JTAG/etc.
  • Integrate VIPs for PCIE/AXI and build
    system stimulus on top of VIP stimulus library.
  • Integrate DIMM model and work with designers
    on phy bring up and implement complex address
    translation functions. 
  • Develop VIPs for complex proprietary protocols. 
  • Execute coverage for verification closure, conduct reviews.
  • Develop and maintain regressions, tools, infrastructure.
  • Measure performance and work with architects and designers to meet the spec.
  • Write verification firmware, bring up real firmware.
  • Functional bring up and debug support on FPGA/emulation platform.
  • Work with Architects and Designers to deliver bug free SOC.
  • Close the full verification cycle of block/subsystem/full chip/multi chip.
  • Support post-silicon bring up.


We are looking for


Passionate about solving complex problems through
highly independent hands-on work with cutting-edge
verification tools, flows and methodologies.

Experience in creating verification environment from scratch
for IP/SubSystem/SOC using Verilog, System Verilog,
UVM, C/C++, perl, python.

Proven experience in full chip verification from
the plan development to tape-out sign-off.

Strong written and verbal communication skills
for strong collaboration with verification, design,
architecture teams.

It is plus if you have 

Expertise in using Cadence tools - Xcelium,
experience using vManager, waveform debug tool 

Experience  in verifying system architecture including,
Memory subsystems , IO peripherals(SPI/UART/I3C/JTAG),
bus protocols (AXI/APB/AHB), PCIE, PHY, NOC, interconnects,
Fabrics, RISC-V based designs, CPU clusters, accelerators.

Experience in leadership and mentoring team members.

It is a big plus if you have 

Experience with formal verification 

Experience with PCIe v5 or v6

Experience with: SATA, Ethernet, PHY, DLL, TL, CXL

Experience with Physical Layer, Data Link Layer, Transaction Layer

What we offer

  • People – the best part of Fittico
  • Freedom where and when you deliver your work
  • Tuition reimbursement, conference allowance 
  • Competitive compensation package

About Fittico

Fittico was founded 2012 with the mission to bring technological and product development excellence to the market, based in Switzerland and south Europe, combining great weather with the Alps 🙂

We have gathered some of the strongest talent in the Europe for our past and current products and projects. We are product building  shop where we mostly work on our own products, the way we believe they should be done. We also collaborate with partners across Europe and North America to bring some of those products to markets. We value integrity and simplicity above all.

Join us

If you believe there is space for personal and professional growth and you crave to be challenged with technology products, while having all the freedom on how to deliver those, consider joining us.